1. Field of Invention
The present invention relates to an active matrix substrate. More particularly, the present invention relates to an active matrix substrate with bypass-lines.
2. Description of Related Art
To meet the life style today, the volumes of video apparatuses are getting smaller and lighter. Though the conventional cathode ray tube (CRT) display still has its advantages, the volume thereof is considered bulky and space-consuming because of the internal electron gun structure thereof. Besides, radiant rays are generated while the CRT display output images, which may injure the viewer's eyes. Accordingly, flat panel display (FPD), for example, liquid crystal display (LCD), developed with optoelectronic technology and semiconductor technology has become the mainstream of display products.
FIG. 1A is a structural diagram of a conventional LCD panel. FIG. 1B is a partial enlarged view of the region S10 of the TFT substrate in FIG. 1A. FIG. 1C is a partial enlarged view of the region S20 of the TFT substrate. in FIG. 1A. First, referring to FIG. 1A, the conventional LCD panel 100 includes a TFT substrate 110, a color filter substrate 120, a printed circuit board 130, a plurality of gate driver ICs 140, and a plurality of data driver ICs 150. The color filter substrate 120 is disposed over the TFT substrate 110. A plurality of data driver ICs 150 are disposed on the printed circuit board 130 and are connected to the data lines (denoted DL in FIG. 1C) of the TFT substrate 110. In addition, the gate driver ICs 140 are connected to the scan lines (denoted SL in FIGS. 1B and 1C) of the TFT substrate 110, and the data driver ICs 150 on the printed circuit board 130 and the gate driver ICs 140 are used for driving the pixel array 20 of the TFT substrate 110.
Referring to FIGS. 1B and 1C again, the foregoing TFT substrate 110 includes a glass substrate 10, a pixel array 20, a peripheral circuit 30, a plurality of shorting bars 40, 50, and a plurality of jumper wires 60. The pixel array 20, the peripheral circuit 30, the shorting bars 40, 50, and the jumper wires 60 are all disposed on the glass substrate 10.
The pixel array 20 comprises a plurality of thin film transistors 22, a plurality of pixel electrodes 24, a plurality of scan lines SL, and a plurality of data lines DL. Each of the thin film transistors 22 is electrically connected to the corresponding scan line SL and data line DL, and each of the pixel electrodes 24 is electrically connected to the corresponding thin film transistor 22.
The peripheral circuit 30 includes a plurality of signal lines 32, a plurality of chip bonding pads 33, a plurality of dummy bonding pads 34, and a plurality of bypass-lines 35, 36. The chip bonding pads 33, for bonding the gate driver ICs 140 and the TFT substrate 110, are located between the bypass-lines 35, 36 and the pixel array 20 and electrically connected to the scan lines SL respectively. The gate driver ICs 140 bonded with the TFT substrate 110 are electrically connected to each other in a cascade through signal lines 32. The shorting bar 40 connects all odd jumper wires 60, and another shorting bar 50 connects all even jumper wires 60. The chip bonding pads 33 are connected between the jumper wires 60 and the scan lines SL. Please note that the bypass-lines 35, 36 are located between the shorting bars 40, 50 and the signal lines 32, and are electrically connected to the corresponding signal lines 32 respectively. The dummy bonding pads 34 are electrically insulated from the pixel array 20 and are located at the outside of the chip bonding pads 33.
To drive the pixel array 20 on the LCD panel 100, relative circuits and chips have to be fabricated around the LCD panel 100 so that voltages and signals can be supplied to the scan lines SL and data lines DL of the pixel array 20. The printed circuit board 130 as shown in FIG. 1A is electrically connected to the data lines DL of the TFT substrate 110 so that data signals can be supplied to the data lines DL. In addition, the plurality of gate driver ICs 140 are bonded on the glass substrate 10 of the TFT substrate 110 using chip on glass (COG) technology, and the gate driver ICs 140 are electrically connected with the scan lines SL of the TFT substrate 110 so that scan signals can be supplied to the scan lines SL.
Please note that the exposed surface area at the left side of the TFT substrate 110 is very long and narrow after the color filter substrate 120 is disposed on the TFT substrate 110, and the gate driver ICs 140 are thus bonded on the TFT substrate 110 in a cascade by the signal lines 32 (as shown in FIG. 1A). However, the impedance of the signal lines 32 may cause voltage attenuation while transmitting relative voltages to the gate driver ICs 140; such situation may be worse in large LCD panels. To avoid the difference in the voltages transmitted to the gate driver ICs 140, the plurality of bypass-lines 35, 36 are disposed beside each gate driver IC 140 (as shown in FIG. 1A), and thus voltages supplied to every gate driver ICs 140 are the same. The detail description of such technology can be referred to the documents of the Patent No. TW 589598 and U.S. Pat. No. 6,844,629.
Referring to FIG. 1B again, a short circuit due to dropping foreign matter or other process factors is unavoidable in the fabricating process of the active matrix substrate 110. For example, in a fabricating process, if foreign objects drop at points A and B denoted in FIG. 1B, the jumper wires 60 located at points A and B are shorted with the bypass-lines 35 and 36 under the two jumper wires 60, respectively. However, the two jumper wires are short-circuited through the shorting bars 40, and therefore the two bypass-lines 35 and 36 under the points A and B may be short-circuited. During a array test, the testing probe is pressed against the dummy bonding pads 34 and a portion of the chip bonding pads 33 (the chip bonding pads 33 connected to the scan lines SL); since the bypass-lines 35 and 36 are not electrically connected to the dummy bonding pads 34 or the chip bonding pads 33 pressed by the probe (the chip bonding pad 33 connected to the scan lines SL), the voltage signals of the bypass-lines 35 and 36 can not be detected; accordingly, whether there is a short circuit between the bypass-lines 35 and 36 can not be detected. Generally speaking, the shorting bars 40 and 50 on the TFT substrate 110 remain after cell processes. During a cell test, since the testing machine uses the probe of, for example, tape automatic bonding (TAB) to test, the probe is directly pressed against the chip bonding pads 33 connected with the scan lines SL, thus whether there is a short circuit between the bypass-lines 35 and 36 can not be detected. After the TFT substrate 110 with a short circuit between the bypass-lines 35 and 36 and the color filter substrate 120 are assembled and filled with liquid crystal, the bonding process is performed. The printed circuit board 130 and the gate driver ICs 140 are bonded on the TFT substrate 110, and then the LCD panel 100 is completed. However, the display quality of the LCD panel 100 is not ideal when a module test is performed to the LCD panel 100 due to the short circuit between the bypass-lines 35 and 36. In other words, the short circuit between the bypass-lines 35 and 36 can only be detected during the module test. In addition, since the short circuit between the bypass-lines 35 and 36 is not detected during the array test, subsequent processes are performed continuously to fabricate the problematic TFT substrate 110, which does not only waste productivity, but also increases the manufacturing cost of the LCD panel 100.